1. Field of the Invention
The present invention relates to data processing systems, and more particularly to apparatus for the computation of sign bit and sign extension in the floating-point unit of a microprocessor.
2. Background Art
U.S. Pat. No. 4,823,260 of Imel et al. describes a microprocessor and a floating-point unit in the processor that implements the IEEE microprocessor floating-point standard P754. Extended-precision floating-point calculations are performed by using 32-bit, 64-bit, and 80-bit real values.
The 80-bit real values are used internally by 80-bit floating-point registers for extremely high-precision calculations. Ordinarily this arithmetic capability would require separate op codes for each instruction which specifies a floating-point data type. This would ordinarily result in a number of separate op codes in order to achieve all possible combinations of floating-point-data types.
The above-cited patent reduced the number of floating-point simplified the programming, thereby increasing the performance of the floating-point operations by providing an apparatus for performing a number of kinds of mixed-precision calculations utilizing a single-instruction op code. The advantage is that mixed-precision arithmetic is supported as well as extended-precision arithmetic. Mixed-precision arithmetic avoids extra conversion instructions, allows computation of the result to sufficient precision instead of the widest precision and does not occur double-rounding in the arithmetic operation if the intermediate result is rounded to extended precision first.
A signed bit located at the high-order bit of a numeric representation contains an indication of the algebraic sign of the number stored in the remaining bits. Sign extension performs a data conversion to a larger format in which extra-bit positions are filled with the value of the sign to thereby preserve the value of signed integers.
In the above Imel. et al. patent, signed and unsigned integer multiply is not done in the floating-point unit. Since the floating-point multiply and the integer multiply do not share the same hardware, a large die size results.
It is an object of the present invention to provide a floating-point-unit in which floating-point multiply and signed and unsigned integer multiply share the same hardware.